-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"

-- DATE "12/11/2021 23:33:00"

-- 
-- Device: Altera EP4CGX15BF14C6 Package FBGA169
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY ALTERA;
LIBRARY CYCLONEIV;
LIBRARY IEEE;
USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
USE CYCLONEIV.CYCLONEIV_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	total IS
    PORT (
	rst : IN std_logic;
	clk : IN std_logic;
	out1 : OUT std_logic_vector(6 DOWNTO 0);
	out2 : OUT std_logic_vector(6 DOWNTO 0);
	h : BUFFER std_logic_vector(3 DOWNTO 0);
	l : BUFFER std_logic_vector(3 DOWNTO 0)
	);
END total;

-- Design Ports Information
-- out1[0]	=>  Location: PIN_H12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- out1[1]	=>  Location: PIN_D11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- out1[2]	=>  Location: PIN_E13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- out1[3]	=>  Location: PIN_A13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- out1[4]	=>  Location: PIN_C11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- out1[5]	=>  Location: PIN_H10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- out1[6]	=>  Location: PIN_F9,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- out2[0]	=>  Location: PIN_D13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- out2[1]	=>  Location: PIN_J13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- out2[2]	=>  Location: PIN_D12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- out2[3]	=>  Location: PIN_F10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- out2[4]	=>  Location: PIN_L13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- out2[5]	=>  Location: PIN_C12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- out2[6]	=>  Location: PIN_F11,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- h[0]	=>  Location: PIN_E10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- h[1]	=>  Location: PIN_D10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- h[2]	=>  Location: PIN_G9,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- h[3]	=>  Location: PIN_G10,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- l[0]	=>  Location: PIN_B13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- l[1]	=>  Location: PIN_L12,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- l[2]	=>  Location: PIN_C13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- l[3]	=>  Location: PIN_K13,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- rst	=>  Location: PIN_J6,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- clk	=>  Location: PIN_J7,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF total IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_rst : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_out1 : std_logic_vector(6 DOWNTO 0);
SIGNAL ww_out2 : std_logic_vector(6 DOWNTO 0);
SIGNAL ww_h : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_l : std_logic_vector(3 DOWNTO 0);
SIGNAL \rst~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \clk~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \div1|clkout~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \out1[0]~output_o\ : std_logic;
SIGNAL \out1[1]~output_o\ : std_logic;
SIGNAL \out1[2]~output_o\ : std_logic;
SIGNAL \out1[3]~output_o\ : std_logic;
SIGNAL \out1[4]~output_o\ : std_logic;
SIGNAL \out1[5]~output_o\ : std_logic;
SIGNAL \out1[6]~output_o\ : std_logic;
SIGNAL \out2[0]~output_o\ : std_logic;
SIGNAL \out2[1]~output_o\ : std_logic;
SIGNAL \out2[2]~output_o\ : std_logic;
SIGNAL \out2[3]~output_o\ : std_logic;
SIGNAL \out2[4]~output_o\ : std_logic;
SIGNAL \out2[5]~output_o\ : std_logic;
SIGNAL \out2[6]~output_o\ : std_logic;
SIGNAL \h[0]~output_o\ : std_logic;
SIGNAL \h[1]~output_o\ : std_logic;
SIGNAL \h[2]~output_o\ : std_logic;
SIGNAL \h[3]~output_o\ : std_logic;
SIGNAL \l[0]~output_o\ : std_logic;
SIGNAL \l[1]~output_o\ : std_logic;
SIGNAL \l[2]~output_o\ : std_logic;
SIGNAL \l[3]~output_o\ : std_logic;
SIGNAL \clk~input_o\ : std_logic;
SIGNAL \clk~inputclkctrl_outclk\ : std_logic;
SIGNAL \div1|Add0~0_combout\ : std_logic;
SIGNAL \div1|Add0~1\ : std_logic;
SIGNAL \div1|Add0~2_combout\ : std_logic;
SIGNAL \div1|Add0~3\ : std_logic;
SIGNAL \div1|Add0~4_combout\ : std_logic;
SIGNAL \div1|Add0~5\ : std_logic;
SIGNAL \div1|Add0~6_combout\ : std_logic;
SIGNAL \div1|Add0~7\ : std_logic;
SIGNAL \div1|Add0~8_combout\ : std_logic;
SIGNAL \div1|Equal0~3_combout\ : std_logic;
SIGNAL \div1|Add0~9\ : std_logic;
SIGNAL \div1|Add0~10_combout\ : std_logic;
SIGNAL \div1|Add0~11\ : std_logic;
SIGNAL \div1|Add0~12_combout\ : std_logic;
SIGNAL \div1|divcnt~3_combout\ : std_logic;
SIGNAL \div1|Add0~13\ : std_logic;
SIGNAL \div1|Add0~14_combout\ : std_logic;
SIGNAL \div1|Add0~15\ : std_logic;
SIGNAL \div1|Add0~16_combout\ : std_logic;
SIGNAL \div1|divcnt~2_combout\ : std_logic;
SIGNAL \div1|Add0~17\ : std_logic;
SIGNAL \div1|Add0~18_combout\ : std_logic;
SIGNAL \div1|divcnt~1_combout\ : std_logic;
SIGNAL \div1|Add0~19\ : std_logic;
SIGNAL \div1|Add0~20_combout\ : std_logic;
SIGNAL \div1|Add0~21\ : std_logic;
SIGNAL \div1|Add0~22_combout\ : std_logic;
SIGNAL \div1|divcnt~0_combout\ : std_logic;
SIGNAL \div1|Add0~23\ : std_logic;
SIGNAL \div1|Add0~24_combout\ : std_logic;
SIGNAL \div1|Add0~25\ : std_logic;
SIGNAL \div1|Add0~26_combout\ : std_logic;
SIGNAL \div1|Add0~27\ : std_logic;
SIGNAL \div1|Add0~28_combout\ : std_logic;
SIGNAL \div1|divcnt~4_combout\ : std_logic;
SIGNAL \div1|Add0~29\ : std_logic;
SIGNAL \div1|Add0~30_combout\ : std_logic;
SIGNAL \div1|Equal0~4_combout\ : std_logic;
SIGNAL \div1|Equal0~1_combout\ : std_logic;
SIGNAL \div1|Equal0~0_combout\ : std_logic;
SIGNAL \div1|Equal0~2_combout\ : std_logic;
SIGNAL \div1|Add0~31\ : std_logic;
SIGNAL \div1|Add0~32_combout\ : std_logic;
SIGNAL \div1|Add0~33\ : std_logic;
SIGNAL \div1|Add0~34_combout\ : std_logic;
SIGNAL \div1|Add0~35\ : std_logic;
SIGNAL \div1|Add0~36_combout\ : std_logic;
SIGNAL \div1|divcnt~5_combout\ : std_logic;
SIGNAL \div1|Add0~37\ : std_logic;
SIGNAL \div1|Add0~38_combout\ : std_logic;
SIGNAL \div1|divcnt~6_combout\ : std_logic;
SIGNAL \div1|Add0~39\ : std_logic;
SIGNAL \div1|Add0~40_combout\ : std_logic;
SIGNAL \div1|Add0~41\ : std_logic;
SIGNAL \div1|Add0~42_combout\ : std_logic;
SIGNAL \div1|Add0~43\ : std_logic;
SIGNAL \div1|Add0~44_combout\ : std_logic;
SIGNAL \div1|divcnt~7_combout\ : std_logic;
SIGNAL \div1|Add0~45\ : std_logic;
SIGNAL \div1|Add0~46_combout\ : std_logic;
SIGNAL \div1|Add0~47\ : std_logic;
SIGNAL \div1|Add0~48_combout\ : std_logic;
SIGNAL \div1|Add0~49\ : std_logic;
SIGNAL \div1|Add0~50_combout\ : std_logic;
SIGNAL \div1|Add0~51\ : std_logic;
SIGNAL \div1|Add0~52_combout\ : std_logic;
SIGNAL \div1|Add0~53\ : std_logic;
SIGNAL \div1|Add0~54_combout\ : std_logic;
SIGNAL \div1|Equal0~7_combout\ : std_logic;
SIGNAL \div1|Equal0~6_combout\ : std_logic;
SIGNAL \div1|Add0~55\ : std_logic;
SIGNAL \div1|Add0~56_combout\ : std_logic;
SIGNAL \div1|Add0~57\ : std_logic;
SIGNAL \div1|Add0~58_combout\ : std_logic;
SIGNAL \div1|Add0~59\ : std_logic;
SIGNAL \div1|Add0~60_combout\ : std_logic;
SIGNAL \div1|Add0~61\ : std_logic;
SIGNAL \div1|Add0~62_combout\ : std_logic;
SIGNAL \div1|Equal0~8_combout\ : std_logic;
SIGNAL \div1|Equal0~5_combout\ : std_logic;
SIGNAL \div1|Equal0~9_combout\ : std_logic;
SIGNAL \div1|Equal0~10_combout\ : std_logic;
SIGNAL \div1|clkout~feeder_combout\ : std_logic;
SIGNAL \div1|clkout~q\ : std_logic;
SIGNAL \div1|clkout~clkctrl_outclk\ : std_logic;
SIGNAL \cnt1|cntout1[0]~3_combout\ : std_logic;
SIGNAL \rst~input_o\ : std_logic;
SIGNAL \rst~inputclkctrl_outclk\ : std_logic;
SIGNAL \cnt1|cntout2[0]~3_combout\ : std_logic;
SIGNAL \cnt1|cntout2[2]~1_combout\ : std_logic;
SIGNAL \cnt1|cntout2~2_combout\ : std_logic;
SIGNAL \cnt1|cntout2~0_combout\ : std_logic;
SIGNAL \cnt1|Equal0~0_combout\ : std_logic;
SIGNAL \cnt1|cntout1[2]~1_combout\ : std_logic;
SIGNAL \cnt1|cntout1~2_combout\ : std_logic;
SIGNAL \cnt1|cntout1~0_combout\ : std_logic;
SIGNAL \dec|Mux6~0_combout\ : std_logic;
SIGNAL \dec|Mux5~0_combout\ : std_logic;
SIGNAL \dec|Mux4~0_combout\ : std_logic;
SIGNAL \dec|Mux3~0_combout\ : std_logic;
SIGNAL \dec|Mux2~0_combout\ : std_logic;
SIGNAL \dec|Mux1~0_combout\ : std_logic;
SIGNAL \dec|Mux0~0_combout\ : std_logic;
SIGNAL \dec|Mux13~0_combout\ : std_logic;
SIGNAL \dec|Mux12~0_combout\ : std_logic;
SIGNAL \dec|Mux11~0_combout\ : std_logic;
SIGNAL \dec|Mux10~0_combout\ : std_logic;
SIGNAL \dec|Mux9~0_combout\ : std_logic;
SIGNAL \dec|Mux8~0_combout\ : std_logic;
SIGNAL \dec|Mux7~0_combout\ : std_logic;
SIGNAL \div1|divcnt\ : std_logic_vector(31 DOWNTO 0);
SIGNAL \cnt1|cntout2\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \cnt1|cntout1\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \ALT_INV_rst~inputclkctrl_outclk\ : std_logic;
SIGNAL \dec|ALT_INV_Mux7~0_combout\ : std_logic;
SIGNAL \dec|ALT_INV_Mux8~0_combout\ : std_logic;
SIGNAL \dec|ALT_INV_Mux9~0_combout\ : std_logic;
SIGNAL \dec|ALT_INV_Mux10~0_combout\ : std_logic;
SIGNAL \dec|ALT_INV_Mux11~0_combout\ : std_logic;
SIGNAL \dec|ALT_INV_Mux12~0_combout\ : std_logic;
SIGNAL \dec|ALT_INV_Mux0~0_combout\ : std_logic;
SIGNAL \dec|ALT_INV_Mux1~0_combout\ : std_logic;
SIGNAL \dec|ALT_INV_Mux2~0_combout\ : std_logic;
SIGNAL \dec|ALT_INV_Mux3~0_combout\ : std_logic;
SIGNAL \dec|ALT_INV_Mux4~0_combout\ : std_logic;
SIGNAL \dec|ALT_INV_Mux5~0_combout\ : std_logic;

BEGIN

ww_rst <= rst;
ww_clk <= clk;
out1 <= ww_out1;
out2 <= ww_out2;
h <= ww_h;
l <= ww_l;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\rst~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \rst~input_o\);

\clk~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \clk~input_o\);

\div1|clkout~clkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \div1|clkout~q\);
\ALT_INV_rst~inputclkctrl_outclk\ <= NOT \rst~inputclkctrl_outclk\;
\dec|ALT_INV_Mux7~0_combout\ <= NOT \dec|Mux7~0_combout\;
\dec|ALT_INV_Mux8~0_combout\ <= NOT \dec|Mux8~0_combout\;
\dec|ALT_INV_Mux9~0_combout\ <= NOT \dec|Mux9~0_combout\;
\dec|ALT_INV_Mux10~0_combout\ <= NOT \dec|Mux10~0_combout\;
\dec|ALT_INV_Mux11~0_combout\ <= NOT \dec|Mux11~0_combout\;
\dec|ALT_INV_Mux12~0_combout\ <= NOT \dec|Mux12~0_combout\;
\dec|ALT_INV_Mux0~0_combout\ <= NOT \dec|Mux0~0_combout\;
\dec|ALT_INV_Mux1~0_combout\ <= NOT \dec|Mux1~0_combout\;
\dec|ALT_INV_Mux2~0_combout\ <= NOT \dec|Mux2~0_combout\;
\dec|ALT_INV_Mux3~0_combout\ <= NOT \dec|Mux3~0_combout\;
\dec|ALT_INV_Mux4~0_combout\ <= NOT \dec|Mux4~0_combout\;
\dec|ALT_INV_Mux5~0_combout\ <= NOT \dec|Mux5~0_combout\;

-- Location: IOOBUF_X33_Y14_N9
\out1[0]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dec|Mux6~0_combout\,
	devoe => ww_devoe,
	o => \out1[0]~output_o\);

-- Location: IOOBUF_X33_Y28_N2
\out1[1]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dec|ALT_INV_Mux5~0_combout\,
	devoe => ww_devoe,
	o => \out1[1]~output_o\);

-- Location: IOOBUF_X33_Y25_N9
\out1[2]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dec|ALT_INV_Mux4~0_combout\,
	devoe => ww_devoe,
	o => \out1[2]~output_o\);

-- Location: IOOBUF_X26_Y31_N2
\out1[3]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dec|ALT_INV_Mux3~0_combout\,
	devoe => ww_devoe,
	o => \out1[3]~output_o\);

-- Location: IOOBUF_X31_Y31_N2
\out1[4]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dec|ALT_INV_Mux2~0_combout\,
	devoe => ww_devoe,
	o => \out1[4]~output_o\);

-- Location: IOOBUF_X33_Y14_N2
\out1[5]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dec|ALT_INV_Mux1~0_combout\,
	devoe => ww_devoe,
	o => \out1[5]~output_o\);

-- Location: IOOBUF_X33_Y25_N2
\out1[6]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dec|ALT_INV_Mux0~0_combout\,
	devoe => ww_devoe,
	o => \out1[6]~output_o\);

-- Location: IOOBUF_X29_Y31_N9
\out2[0]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dec|Mux13~0_combout\,
	devoe => ww_devoe,
	o => \out2[0]~output_o\);

-- Location: IOOBUF_X33_Y15_N9
\out2[1]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dec|ALT_INV_Mux12~0_combout\,
	devoe => ww_devoe,
	o => \out2[1]~output_o\);

-- Location: IOOBUF_X33_Y28_N9
\out2[2]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dec|ALT_INV_Mux11~0_combout\,
	devoe => ww_devoe,
	o => \out2[2]~output_o\);

-- Location: IOOBUF_X33_Y24_N2
\out2[3]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dec|ALT_INV_Mux10~0_combout\,
	devoe => ww_devoe,
	o => \out2[3]~output_o\);

-- Location: IOOBUF_X33_Y12_N9
\out2[4]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dec|ALT_INV_Mux9~0_combout\,
	devoe => ww_devoe,
	o => \out2[4]~output_o\);

-- Location: IOOBUF_X31_Y31_N9
\out2[5]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dec|ALT_INV_Mux8~0_combout\,
	devoe => ww_devoe,
	o => \out2[5]~output_o\);

-- Location: IOOBUF_X33_Y24_N9
\out2[6]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \dec|ALT_INV_Mux7~0_combout\,
	devoe => ww_devoe,
	o => \out2[6]~output_o\);

-- Location: IOOBUF_X33_Y27_N2
\h[0]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \cnt1|cntout1\(0),
	devoe => ww_devoe,
	o => \h[0]~output_o\);

-- Location: IOOBUF_X33_Y27_N9
\h[1]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \cnt1|cntout1\(1),
	devoe => ww_devoe,
	o => \h[1]~output_o\);

-- Location: IOOBUF_X33_Y22_N2
\h[2]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \cnt1|cntout1\(2),
	devoe => ww_devoe,
	o => \h[2]~output_o\);

-- Location: IOOBUF_X33_Y22_N9
\h[3]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \cnt1|cntout1\(3),
	devoe => ww_devoe,
	o => \h[3]~output_o\);

-- Location: IOOBUF_X26_Y31_N9
\l[0]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \cnt1|cntout2\(0),
	devoe => ww_devoe,
	o => \l[0]~output_o\);

-- Location: IOOBUF_X33_Y12_N2
\l[1]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \cnt1|cntout2\(1),
	devoe => ww_devoe,
	o => \l[1]~output_o\);

-- Location: IOOBUF_X29_Y31_N2
\l[2]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \cnt1|cntout2\(2),
	devoe => ww_devoe,
	o => \l[2]~output_o\);

-- Location: IOOBUF_X33_Y15_N2
\l[3]~output\ : cycloneiv_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \cnt1|cntout2\(3),
	devoe => ww_devoe,
	o => \l[3]~output_o\);

-- Location: IOIBUF_X16_Y0_N15
\clk~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_clk,
	o => \clk~input_o\);

-- Location: CLKCTRL_G17
\clk~inputclkctrl\ : cycloneiv_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \clk~inputclkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \clk~inputclkctrl_outclk\);

-- Location: LCCOMB_X15_Y6_N0
\div1|Add0~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~0_combout\ = \div1|divcnt\(0) $ (VCC)
-- \div1|Add0~1\ = CARRY(\div1|divcnt\(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(0),
	datad => VCC,
	combout => \div1|Add0~0_combout\,
	cout => \div1|Add0~1\);

-- Location: FF_X15_Y6_N1
\div1|divcnt[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(0));

-- Location: LCCOMB_X15_Y6_N2
\div1|Add0~2\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~2_combout\ = (\div1|divcnt\(1) & (!\div1|Add0~1\)) # (!\div1|divcnt\(1) & ((\div1|Add0~1\) # (GND)))
-- \div1|Add0~3\ = CARRY((!\div1|Add0~1\) # (!\div1|divcnt\(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(1),
	datad => VCC,
	cin => \div1|Add0~1\,
	combout => \div1|Add0~2_combout\,
	cout => \div1|Add0~3\);

-- Location: FF_X15_Y6_N3
\div1|divcnt[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(1));

-- Location: LCCOMB_X15_Y6_N4
\div1|Add0~4\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~4_combout\ = (\div1|divcnt\(2) & (\div1|Add0~3\ $ (GND))) # (!\div1|divcnt\(2) & (!\div1|Add0~3\ & VCC))
-- \div1|Add0~5\ = CARRY((\div1|divcnt\(2) & !\div1|Add0~3\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(2),
	datad => VCC,
	cin => \div1|Add0~3\,
	combout => \div1|Add0~4_combout\,
	cout => \div1|Add0~5\);

-- Location: FF_X15_Y6_N5
\div1|divcnt[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~4_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(2));

-- Location: LCCOMB_X15_Y6_N6
\div1|Add0~6\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~6_combout\ = (\div1|divcnt\(3) & (!\div1|Add0~5\)) # (!\div1|divcnt\(3) & ((\div1|Add0~5\) # (GND)))
-- \div1|Add0~7\ = CARRY((!\div1|Add0~5\) # (!\div1|divcnt\(3)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(3),
	datad => VCC,
	cin => \div1|Add0~5\,
	combout => \div1|Add0~6_combout\,
	cout => \div1|Add0~7\);

-- Location: FF_X15_Y6_N7
\div1|divcnt[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~6_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(3));

-- Location: LCCOMB_X15_Y6_N8
\div1|Add0~8\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~8_combout\ = (\div1|divcnt\(4) & (\div1|Add0~7\ $ (GND))) # (!\div1|divcnt\(4) & (!\div1|Add0~7\ & VCC))
-- \div1|Add0~9\ = CARRY((\div1|divcnt\(4) & !\div1|Add0~7\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(4),
	datad => VCC,
	cin => \div1|Add0~7\,
	combout => \div1|Add0~8_combout\,
	cout => \div1|Add0~9\);

-- Location: FF_X15_Y6_N9
\div1|divcnt[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~8_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(4));

-- Location: LCCOMB_X16_Y6_N30
\div1|Equal0~3\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Equal0~3_combout\ = (\div1|divcnt\(4) & (\div1|divcnt\(2) & (\div1|divcnt\(3) & \div1|divcnt\(1))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(4),
	datab => \div1|divcnt\(2),
	datac => \div1|divcnt\(3),
	datad => \div1|divcnt\(1),
	combout => \div1|Equal0~3_combout\);

-- Location: LCCOMB_X15_Y6_N10
\div1|Add0~10\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~10_combout\ = (\div1|divcnt\(5) & (!\div1|Add0~9\)) # (!\div1|divcnt\(5) & ((\div1|Add0~9\) # (GND)))
-- \div1|Add0~11\ = CARRY((!\div1|Add0~9\) # (!\div1|divcnt\(5)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(5),
	datad => VCC,
	cin => \div1|Add0~9\,
	combout => \div1|Add0~10_combout\,
	cout => \div1|Add0~11\);

-- Location: FF_X15_Y6_N11
\div1|divcnt[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(5));

-- Location: LCCOMB_X15_Y6_N12
\div1|Add0~12\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~12_combout\ = (\div1|divcnt\(6) & (\div1|Add0~11\ $ (GND))) # (!\div1|divcnt\(6) & (!\div1|Add0~11\ & VCC))
-- \div1|Add0~13\ = CARRY((\div1|divcnt\(6) & !\div1|Add0~11\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100001010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(6),
	datad => VCC,
	cin => \div1|Add0~11\,
	combout => \div1|Add0~12_combout\,
	cout => \div1|Add0~13\);

-- Location: LCCOMB_X16_Y6_N20
\div1|divcnt~3\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|divcnt~3_combout\ = (\div1|Add0~12_combout\ & !\div1|Equal0~10_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \div1|Add0~12_combout\,
	datad => \div1|Equal0~10_combout\,
	combout => \div1|divcnt~3_combout\);

-- Location: FF_X16_Y6_N21
\div1|divcnt[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|divcnt~3_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(6));

-- Location: LCCOMB_X15_Y6_N14
\div1|Add0~14\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~14_combout\ = (\div1|divcnt\(7) & (!\div1|Add0~13\)) # (!\div1|divcnt\(7) & ((\div1|Add0~13\) # (GND)))
-- \div1|Add0~15\ = CARRY((!\div1|Add0~13\) # (!\div1|divcnt\(7)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(7),
	datad => VCC,
	cin => \div1|Add0~13\,
	combout => \div1|Add0~14_combout\,
	cout => \div1|Add0~15\);

-- Location: FF_X15_Y6_N15
\div1|divcnt[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~14_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(7));

-- Location: LCCOMB_X15_Y6_N16
\div1|Add0~16\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~16_combout\ = (\div1|divcnt\(8) & (\div1|Add0~15\ $ (GND))) # (!\div1|divcnt\(8) & (!\div1|Add0~15\ & VCC))
-- \div1|Add0~17\ = CARRY((\div1|divcnt\(8) & !\div1|Add0~15\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(8),
	datad => VCC,
	cin => \div1|Add0~15\,
	combout => \div1|Add0~16_combout\,
	cout => \div1|Add0~17\);

-- Location: LCCOMB_X16_Y6_N26
\div1|divcnt~2\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|divcnt~2_combout\ = (\div1|Add0~16_combout\ & !\div1|Equal0~10_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \div1|Add0~16_combout\,
	datad => \div1|Equal0~10_combout\,
	combout => \div1|divcnt~2_combout\);

-- Location: FF_X16_Y6_N27
\div1|divcnt[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|divcnt~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(8));

-- Location: LCCOMB_X15_Y6_N18
\div1|Add0~18\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~18_combout\ = (\div1|divcnt\(9) & (!\div1|Add0~17\)) # (!\div1|divcnt\(9) & ((\div1|Add0~17\) # (GND)))
-- \div1|Add0~19\ = CARRY((!\div1|Add0~17\) # (!\div1|divcnt\(9)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(9),
	datad => VCC,
	cin => \div1|Add0~17\,
	combout => \div1|Add0~18_combout\,
	cout => \div1|Add0~19\);

-- Location: LCCOMB_X16_Y6_N6
\div1|divcnt~1\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|divcnt~1_combout\ = (\div1|Add0~18_combout\ & !\div1|Equal0~10_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \div1|Add0~18_combout\,
	datad => \div1|Equal0~10_combout\,
	combout => \div1|divcnt~1_combout\);

-- Location: FF_X16_Y6_N7
\div1|divcnt[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|divcnt~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(9));

-- Location: LCCOMB_X15_Y6_N20
\div1|Add0~20\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~20_combout\ = (\div1|divcnt\(10) & (\div1|Add0~19\ $ (GND))) # (!\div1|divcnt\(10) & (!\div1|Add0~19\ & VCC))
-- \div1|Add0~21\ = CARRY((\div1|divcnt\(10) & !\div1|Add0~19\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(10),
	datad => VCC,
	cin => \div1|Add0~19\,
	combout => \div1|Add0~20_combout\,
	cout => \div1|Add0~21\);

-- Location: FF_X15_Y6_N21
\div1|divcnt[10]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~20_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(10));

-- Location: LCCOMB_X15_Y6_N22
\div1|Add0~22\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~22_combout\ = (\div1|divcnt\(11) & (!\div1|Add0~21\)) # (!\div1|divcnt\(11) & ((\div1|Add0~21\) # (GND)))
-- \div1|Add0~23\ = CARRY((!\div1|Add0~21\) # (!\div1|divcnt\(11)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(11),
	datad => VCC,
	cin => \div1|Add0~21\,
	combout => \div1|Add0~22_combout\,
	cout => \div1|Add0~23\);

-- Location: LCCOMB_X16_Y6_N4
\div1|divcnt~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|divcnt~0_combout\ = (\div1|Add0~22_combout\ & !\div1|Equal0~10_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \div1|Add0~22_combout\,
	datad => \div1|Equal0~10_combout\,
	combout => \div1|divcnt~0_combout\);

-- Location: FF_X16_Y6_N5
\div1|divcnt[11]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|divcnt~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(11));

-- Location: LCCOMB_X15_Y6_N24
\div1|Add0~24\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~24_combout\ = (\div1|divcnt\(12) & (\div1|Add0~23\ $ (GND))) # (!\div1|divcnt\(12) & (!\div1|Add0~23\ & VCC))
-- \div1|Add0~25\ = CARRY((\div1|divcnt\(12) & !\div1|Add0~23\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(12),
	datad => VCC,
	cin => \div1|Add0~23\,
	combout => \div1|Add0~24_combout\,
	cout => \div1|Add0~25\);

-- Location: FF_X15_Y6_N25
\div1|divcnt[12]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~24_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(12));

-- Location: LCCOMB_X15_Y6_N26
\div1|Add0~26\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~26_combout\ = (\div1|divcnt\(13) & (!\div1|Add0~25\)) # (!\div1|divcnt\(13) & ((\div1|Add0~25\) # (GND)))
-- \div1|Add0~27\ = CARRY((!\div1|Add0~25\) # (!\div1|divcnt\(13)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(13),
	datad => VCC,
	cin => \div1|Add0~25\,
	combout => \div1|Add0~26_combout\,
	cout => \div1|Add0~27\);

-- Location: FF_X15_Y6_N27
\div1|divcnt[13]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~26_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(13));

-- Location: LCCOMB_X15_Y6_N28
\div1|Add0~28\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~28_combout\ = (\div1|divcnt\(14) & (\div1|Add0~27\ $ (GND))) # (!\div1|divcnt\(14) & (!\div1|Add0~27\ & VCC))
-- \div1|Add0~29\ = CARRY((\div1|divcnt\(14) & !\div1|Add0~27\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(14),
	datad => VCC,
	cin => \div1|Add0~27\,
	combout => \div1|Add0~28_combout\,
	cout => \div1|Add0~29\);

-- Location: LCCOMB_X16_Y5_N22
\div1|divcnt~4\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|divcnt~4_combout\ = (\div1|Add0~28_combout\ & !\div1|Equal0~10_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \div1|Add0~28_combout\,
	datad => \div1|Equal0~10_combout\,
	combout => \div1|divcnt~4_combout\);

-- Location: FF_X16_Y5_N23
\div1|divcnt[14]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|divcnt~4_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(14));

-- Location: LCCOMB_X15_Y6_N30
\div1|Add0~30\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~30_combout\ = (\div1|divcnt\(15) & (!\div1|Add0~29\)) # (!\div1|divcnt\(15) & ((\div1|Add0~29\) # (GND)))
-- \div1|Add0~31\ = CARRY((!\div1|Add0~29\) # (!\div1|divcnt\(15)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(15),
	datad => VCC,
	cin => \div1|Add0~29\,
	combout => \div1|Add0~30_combout\,
	cout => \div1|Add0~31\);

-- Location: FF_X15_Y6_N31
\div1|divcnt[15]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~30_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(15));

-- Location: LCCOMB_X16_Y5_N2
\div1|Equal0~4\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Equal0~4_combout\ = (\div1|divcnt\(0) & (!\div1|divcnt\(13) & (\div1|divcnt\(14) & !\div1|divcnt\(15))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(0),
	datab => \div1|divcnt\(13),
	datac => \div1|divcnt\(14),
	datad => \div1|divcnt\(15),
	combout => \div1|Equal0~4_combout\);

-- Location: LCCOMB_X16_Y6_N22
\div1|Equal0~1\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Equal0~1_combout\ = (!\div1|divcnt\(6) & \div1|divcnt\(5))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(6),
	datad => \div1|divcnt\(5),
	combout => \div1|Equal0~1_combout\);

-- Location: LCCOMB_X16_Y6_N0
\div1|Equal0~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Equal0~0_combout\ = (\div1|divcnt\(9) & (!\div1|divcnt\(10) & (\div1|divcnt\(11) & !\div1|divcnt\(12))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(9),
	datab => \div1|divcnt\(10),
	datac => \div1|divcnt\(11),
	datad => \div1|divcnt\(12),
	combout => \div1|Equal0~0_combout\);

-- Location: LCCOMB_X16_Y6_N12
\div1|Equal0~2\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Equal0~2_combout\ = (!\div1|divcnt\(7) & (\div1|divcnt\(8) & (\div1|Equal0~1_combout\ & \div1|Equal0~0_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(7),
	datab => \div1|divcnt\(8),
	datac => \div1|Equal0~1_combout\,
	datad => \div1|Equal0~0_combout\,
	combout => \div1|Equal0~2_combout\);

-- Location: LCCOMB_X15_Y5_N0
\div1|Add0~32\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~32_combout\ = (\div1|divcnt\(16) & (\div1|Add0~31\ $ (GND))) # (!\div1|divcnt\(16) & (!\div1|Add0~31\ & VCC))
-- \div1|Add0~33\ = CARRY((\div1|divcnt\(16) & !\div1|Add0~31\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(16),
	datad => VCC,
	cin => \div1|Add0~31\,
	combout => \div1|Add0~32_combout\,
	cout => \div1|Add0~33\);

-- Location: FF_X15_Y5_N1
\div1|divcnt[16]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~32_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(16));

-- Location: LCCOMB_X15_Y5_N2
\div1|Add0~34\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~34_combout\ = (\div1|divcnt\(17) & (!\div1|Add0~33\)) # (!\div1|divcnt\(17) & ((\div1|Add0~33\) # (GND)))
-- \div1|Add0~35\ = CARRY((!\div1|Add0~33\) # (!\div1|divcnt\(17)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(17),
	datad => VCC,
	cin => \div1|Add0~33\,
	combout => \div1|Add0~34_combout\,
	cout => \div1|Add0~35\);

-- Location: FF_X15_Y5_N3
\div1|divcnt[17]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~34_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(17));

-- Location: LCCOMB_X15_Y5_N4
\div1|Add0~36\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~36_combout\ = (\div1|divcnt\(18) & (\div1|Add0~35\ $ (GND))) # (!\div1|divcnt\(18) & (!\div1|Add0~35\ & VCC))
-- \div1|Add0~37\ = CARRY((\div1|divcnt\(18) & !\div1|Add0~35\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(18),
	datad => VCC,
	cin => \div1|Add0~35\,
	combout => \div1|Add0~36_combout\,
	cout => \div1|Add0~37\);

-- Location: LCCOMB_X16_Y5_N18
\div1|divcnt~5\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|divcnt~5_combout\ = (\div1|Add0~36_combout\ & !\div1|Equal0~10_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \div1|Add0~36_combout\,
	datad => \div1|Equal0~10_combout\,
	combout => \div1|divcnt~5_combout\);

-- Location: FF_X16_Y5_N19
\div1|divcnt[18]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|divcnt~5_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(18));

-- Location: LCCOMB_X15_Y5_N6
\div1|Add0~38\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~38_combout\ = (\div1|divcnt\(19) & (!\div1|Add0~37\)) # (!\div1|divcnt\(19) & ((\div1|Add0~37\) # (GND)))
-- \div1|Add0~39\ = CARRY((!\div1|Add0~37\) # (!\div1|divcnt\(19)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(19),
	datad => VCC,
	cin => \div1|Add0~37\,
	combout => \div1|Add0~38_combout\,
	cout => \div1|Add0~39\);

-- Location: LCCOMB_X16_Y5_N6
\div1|divcnt~6\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|divcnt~6_combout\ = (\div1|Add0~38_combout\ & !\div1|Equal0~10_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \div1|Add0~38_combout\,
	datad => \div1|Equal0~10_combout\,
	combout => \div1|divcnt~6_combout\);

-- Location: FF_X16_Y5_N7
\div1|divcnt[19]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|divcnt~6_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(19));

-- Location: LCCOMB_X15_Y5_N8
\div1|Add0~40\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~40_combout\ = (\div1|divcnt\(20) & (\div1|Add0~39\ $ (GND))) # (!\div1|divcnt\(20) & (!\div1|Add0~39\ & VCC))
-- \div1|Add0~41\ = CARRY((\div1|divcnt\(20) & !\div1|Add0~39\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(20),
	datad => VCC,
	cin => \div1|Add0~39\,
	combout => \div1|Add0~40_combout\,
	cout => \div1|Add0~41\);

-- Location: FF_X15_Y5_N9
\div1|divcnt[20]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~40_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(20));

-- Location: LCCOMB_X15_Y5_N10
\div1|Add0~42\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~42_combout\ = (\div1|divcnt\(21) & (!\div1|Add0~41\)) # (!\div1|divcnt\(21) & ((\div1|Add0~41\) # (GND)))
-- \div1|Add0~43\ = CARRY((!\div1|Add0~41\) # (!\div1|divcnt\(21)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(21),
	datad => VCC,
	cin => \div1|Add0~41\,
	combout => \div1|Add0~42_combout\,
	cout => \div1|Add0~43\);

-- Location: FF_X15_Y5_N11
\div1|divcnt[21]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~42_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(21));

-- Location: LCCOMB_X15_Y5_N12
\div1|Add0~44\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~44_combout\ = (\div1|divcnt\(22) & (\div1|Add0~43\ $ (GND))) # (!\div1|divcnt\(22) & (!\div1|Add0~43\ & VCC))
-- \div1|Add0~45\ = CARRY((\div1|divcnt\(22) & !\div1|Add0~43\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(22),
	datad => VCC,
	cin => \div1|Add0~43\,
	combout => \div1|Add0~44_combout\,
	cout => \div1|Add0~45\);

-- Location: LCCOMB_X16_Y5_N26
\div1|divcnt~7\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|divcnt~7_combout\ = (!\div1|Equal0~10_combout\ & \div1|Add0~44_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \div1|Equal0~10_combout\,
	datad => \div1|Add0~44_combout\,
	combout => \div1|divcnt~7_combout\);

-- Location: FF_X16_Y5_N27
\div1|divcnt[22]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|divcnt~7_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(22));

-- Location: LCCOMB_X15_Y5_N14
\div1|Add0~46\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~46_combout\ = (\div1|divcnt\(23) & (!\div1|Add0~45\)) # (!\div1|divcnt\(23) & ((\div1|Add0~45\) # (GND)))
-- \div1|Add0~47\ = CARRY((!\div1|Add0~45\) # (!\div1|divcnt\(23)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(23),
	datad => VCC,
	cin => \div1|Add0~45\,
	combout => \div1|Add0~46_combout\,
	cout => \div1|Add0~47\);

-- Location: FF_X15_Y5_N15
\div1|divcnt[23]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~46_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(23));

-- Location: LCCOMB_X15_Y5_N16
\div1|Add0~48\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~48_combout\ = (\div1|divcnt\(24) & (\div1|Add0~47\ $ (GND))) # (!\div1|divcnt\(24) & (!\div1|Add0~47\ & VCC))
-- \div1|Add0~49\ = CARRY((\div1|divcnt\(24) & !\div1|Add0~47\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(24),
	datad => VCC,
	cin => \div1|Add0~47\,
	combout => \div1|Add0~48_combout\,
	cout => \div1|Add0~49\);

-- Location: FF_X15_Y5_N17
\div1|divcnt[24]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~48_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(24));

-- Location: LCCOMB_X15_Y5_N18
\div1|Add0~50\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~50_combout\ = (\div1|divcnt\(25) & (!\div1|Add0~49\)) # (!\div1|divcnt\(25) & ((\div1|Add0~49\) # (GND)))
-- \div1|Add0~51\ = CARRY((!\div1|Add0~49\) # (!\div1|divcnt\(25)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(25),
	datad => VCC,
	cin => \div1|Add0~49\,
	combout => \div1|Add0~50_combout\,
	cout => \div1|Add0~51\);

-- Location: FF_X15_Y5_N19
\div1|divcnt[25]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~50_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(25));

-- Location: LCCOMB_X15_Y5_N20
\div1|Add0~52\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~52_combout\ = (\div1|divcnt\(26) & (\div1|Add0~51\ $ (GND))) # (!\div1|divcnt\(26) & (!\div1|Add0~51\ & VCC))
-- \div1|Add0~53\ = CARRY((\div1|divcnt\(26) & !\div1|Add0~51\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(26),
	datad => VCC,
	cin => \div1|Add0~51\,
	combout => \div1|Add0~52_combout\,
	cout => \div1|Add0~53\);

-- Location: FF_X15_Y5_N21
\div1|divcnt[26]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~52_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(26));

-- Location: LCCOMB_X15_Y5_N22
\div1|Add0~54\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~54_combout\ = (\div1|divcnt\(27) & (!\div1|Add0~53\)) # (!\div1|divcnt\(27) & ((\div1|Add0~53\) # (GND)))
-- \div1|Add0~55\ = CARRY((!\div1|Add0~53\) # (!\div1|divcnt\(27)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(27),
	datad => VCC,
	cin => \div1|Add0~53\,
	combout => \div1|Add0~54_combout\,
	cout => \div1|Add0~55\);

-- Location: FF_X15_Y5_N23
\div1|divcnt[27]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~54_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(27));

-- Location: LCCOMB_X16_Y5_N12
\div1|Equal0~7\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Equal0~7_combout\ = (!\div1|divcnt\(24) & (!\div1|divcnt\(25) & (!\div1|divcnt\(27) & !\div1|divcnt\(26))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(24),
	datab => \div1|divcnt\(25),
	datac => \div1|divcnt\(27),
	datad => \div1|divcnt\(26),
	combout => \div1|Equal0~7_combout\);

-- Location: LCCOMB_X16_Y5_N28
\div1|Equal0~6\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Equal0~6_combout\ = (!\div1|divcnt\(21) & (!\div1|divcnt\(23) & (\div1|divcnt\(22) & !\div1|divcnt\(20))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(21),
	datab => \div1|divcnt\(23),
	datac => \div1|divcnt\(22),
	datad => \div1|divcnt\(20),
	combout => \div1|Equal0~6_combout\);

-- Location: LCCOMB_X15_Y5_N24
\div1|Add0~56\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~56_combout\ = (\div1|divcnt\(28) & (\div1|Add0~55\ $ (GND))) # (!\div1|divcnt\(28) & (!\div1|Add0~55\ & VCC))
-- \div1|Add0~57\ = CARRY((\div1|divcnt\(28) & !\div1|Add0~55\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(28),
	datad => VCC,
	cin => \div1|Add0~55\,
	combout => \div1|Add0~56_combout\,
	cout => \div1|Add0~57\);

-- Location: FF_X15_Y5_N25
\div1|divcnt[28]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~56_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(28));

-- Location: LCCOMB_X15_Y5_N26
\div1|Add0~58\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~58_combout\ = (\div1|divcnt\(29) & (!\div1|Add0~57\)) # (!\div1|divcnt\(29) & ((\div1|Add0~57\) # (GND)))
-- \div1|Add0~59\ = CARRY((!\div1|Add0~57\) # (!\div1|divcnt\(29)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(29),
	datad => VCC,
	cin => \div1|Add0~57\,
	combout => \div1|Add0~58_combout\,
	cout => \div1|Add0~59\);

-- Location: FF_X15_Y5_N27
\div1|divcnt[29]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~58_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(29));

-- Location: LCCOMB_X15_Y5_N28
\div1|Add0~60\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~60_combout\ = (\div1|divcnt\(30) & (\div1|Add0~59\ $ (GND))) # (!\div1|divcnt\(30) & (!\div1|Add0~59\ & VCC))
-- \div1|Add0~61\ = CARRY((\div1|divcnt\(30) & !\div1|Add0~59\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => \div1|divcnt\(30),
	datad => VCC,
	cin => \div1|Add0~59\,
	combout => \div1|Add0~60_combout\,
	cout => \div1|Add0~61\);

-- Location: FF_X15_Y5_N29
\div1|divcnt[30]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~60_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(30));

-- Location: LCCOMB_X15_Y5_N30
\div1|Add0~62\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Add0~62_combout\ = \div1|divcnt\(31) $ (\div1|Add0~61\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(31),
	cin => \div1|Add0~61\,
	combout => \div1|Add0~62_combout\);

-- Location: FF_X15_Y5_N31
\div1|divcnt[31]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|Add0~62_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|divcnt\(31));

-- Location: LCCOMB_X16_Y5_N4
\div1|Equal0~8\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Equal0~8_combout\ = (!\div1|divcnt\(29) & (!\div1|divcnt\(31) & (!\div1|divcnt\(30) & !\div1|divcnt\(28))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(29),
	datab => \div1|divcnt\(31),
	datac => \div1|divcnt\(30),
	datad => \div1|divcnt\(28),
	combout => \div1|Equal0~8_combout\);

-- Location: LCCOMB_X16_Y5_N20
\div1|Equal0~5\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Equal0~5_combout\ = (!\div1|divcnt\(17) & (\div1|divcnt\(18) & (!\div1|divcnt\(16) & \div1|divcnt\(19))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000010000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \div1|divcnt\(17),
	datab => \div1|divcnt\(18),
	datac => \div1|divcnt\(16),
	datad => \div1|divcnt\(19),
	combout => \div1|Equal0~5_combout\);

-- Location: LCCOMB_X16_Y5_N24
\div1|Equal0~9\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Equal0~9_combout\ = (\div1|Equal0~7_combout\ & (\div1|Equal0~6_combout\ & (\div1|Equal0~8_combout\ & \div1|Equal0~5_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \div1|Equal0~7_combout\,
	datab => \div1|Equal0~6_combout\,
	datac => \div1|Equal0~8_combout\,
	datad => \div1|Equal0~5_combout\,
	combout => \div1|Equal0~9_combout\);

-- Location: LCCOMB_X16_Y5_N0
\div1|Equal0~10\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|Equal0~10_combout\ = (\div1|Equal0~3_combout\ & (\div1|Equal0~4_combout\ & (\div1|Equal0~2_combout\ & \div1|Equal0~9_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \div1|Equal0~3_combout\,
	datab => \div1|Equal0~4_combout\,
	datac => \div1|Equal0~2_combout\,
	datad => \div1|Equal0~9_combout\,
	combout => \div1|Equal0~10_combout\);

-- Location: LCCOMB_X16_Y5_N30
\div1|clkout~feeder\ : cycloneiv_lcell_comb
-- Equation(s):
-- \div1|clkout~feeder_combout\ = \div1|Equal0~10_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \div1|Equal0~10_combout\,
	combout => \div1|clkout~feeder_combout\);

-- Location: FF_X16_Y5_N31
\div1|clkout\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \div1|clkout~feeder_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \div1|clkout~q\);

-- Location: CLKCTRL_G15
\div1|clkout~clkctrl\ : cycloneiv_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \div1|clkout~clkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \div1|clkout~clkctrl_outclk\);

-- Location: LCCOMB_X32_Y24_N0
\cnt1|cntout1[0]~3\ : cycloneiv_lcell_comb
-- Equation(s):
-- \cnt1|cntout1[0]~3_combout\ = !\cnt1|cntout1\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \cnt1|cntout1\(0),
	combout => \cnt1|cntout1[0]~3_combout\);

-- Location: IOIBUF_X16_Y0_N22
\rst~input\ : cycloneiv_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_rst,
	o => \rst~input_o\);

-- Location: CLKCTRL_G19
\rst~inputclkctrl\ : cycloneiv_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \rst~inputclkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \rst~inputclkctrl_outclk\);

-- Location: LCCOMB_X32_Y24_N4
\cnt1|cntout2[0]~3\ : cycloneiv_lcell_comb
-- Equation(s):
-- \cnt1|cntout2[0]~3_combout\ = !\cnt1|cntout2\(0)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \cnt1|cntout2\(0),
	combout => \cnt1|cntout2[0]~3_combout\);

-- Location: FF_X32_Y24_N5
\cnt1|cntout2[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div1|clkout~clkctrl_outclk\,
	d => \cnt1|cntout2[0]~3_combout\,
	clrn => \ALT_INV_rst~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \cnt1|cntout2\(0));

-- Location: LCCOMB_X32_Y24_N28
\cnt1|cntout2[2]~1\ : cycloneiv_lcell_comb
-- Equation(s):
-- \cnt1|cntout2[2]~1_combout\ = \cnt1|cntout2\(2) $ (((\cnt1|cntout2\(1) & \cnt1|cntout2\(0))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111100001111000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout2\(1),
	datab => \cnt1|cntout2\(0),
	datac => \cnt1|cntout2\(2),
	combout => \cnt1|cntout2[2]~1_combout\);

-- Location: FF_X32_Y24_N29
\cnt1|cntout2[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div1|clkout~clkctrl_outclk\,
	d => \cnt1|cntout2[2]~1_combout\,
	clrn => \ALT_INV_rst~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \cnt1|cntout2\(2));

-- Location: LCCOMB_X32_Y24_N14
\cnt1|cntout2~2\ : cycloneiv_lcell_comb
-- Equation(s):
-- \cnt1|cntout2~2_combout\ = (\cnt1|cntout2\(2) & (\cnt1|cntout2\(3) $ (((\cnt1|cntout2\(0) & \cnt1|cntout2\(1)))))) # (!\cnt1|cntout2\(2) & (\cnt1|cntout2\(3) & ((\cnt1|cntout2\(1)) # (!\cnt1|cntout2\(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111100010110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout2\(2),
	datab => \cnt1|cntout2\(0),
	datac => \cnt1|cntout2\(3),
	datad => \cnt1|cntout2\(1),
	combout => \cnt1|cntout2~2_combout\);

-- Location: FF_X32_Y24_N15
\cnt1|cntout2[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div1|clkout~clkctrl_outclk\,
	d => \cnt1|cntout2~2_combout\,
	clrn => \ALT_INV_rst~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \cnt1|cntout2\(3));

-- Location: LCCOMB_X32_Y24_N30
\cnt1|cntout2~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \cnt1|cntout2~0_combout\ = (\cnt1|cntout2\(0) & (!\cnt1|cntout2\(1) & ((\cnt1|cntout2\(2)) # (!\cnt1|cntout2\(3))))) # (!\cnt1|cntout2\(0) & (((\cnt1|cntout2\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011100000111100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout2\(2),
	datab => \cnt1|cntout2\(0),
	datac => \cnt1|cntout2\(1),
	datad => \cnt1|cntout2\(3),
	combout => \cnt1|cntout2~0_combout\);

-- Location: FF_X32_Y24_N31
\cnt1|cntout2[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div1|clkout~clkctrl_outclk\,
	d => \cnt1|cntout2~0_combout\,
	clrn => \ALT_INV_rst~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \cnt1|cntout2\(1));

-- Location: LCCOMB_X32_Y24_N18
\cnt1|Equal0~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \cnt1|Equal0~0_combout\ = (!\cnt1|cntout2\(1) & (\cnt1|cntout2\(0) & (\cnt1|cntout2\(3) & !\cnt1|cntout2\(2))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000001000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout2\(1),
	datab => \cnt1|cntout2\(0),
	datac => \cnt1|cntout2\(3),
	datad => \cnt1|cntout2\(2),
	combout => \cnt1|Equal0~0_combout\);

-- Location: FF_X32_Y24_N1
\cnt1|cntout1[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div1|clkout~clkctrl_outclk\,
	d => \cnt1|cntout1[0]~3_combout\,
	clrn => \ALT_INV_rst~inputclkctrl_outclk\,
	ena => \cnt1|Equal0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \cnt1|cntout1\(0));

-- Location: LCCOMB_X32_Y24_N20
\cnt1|cntout1[2]~1\ : cycloneiv_lcell_comb
-- Equation(s):
-- \cnt1|cntout1[2]~1_combout\ = \cnt1|cntout1\(2) $ (((\cnt1|cntout1\(1) & (\cnt1|cntout1\(0) & \cnt1|Equal0~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111100011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout1\(1),
	datab => \cnt1|cntout1\(0),
	datac => \cnt1|cntout1\(2),
	datad => \cnt1|Equal0~0_combout\,
	combout => \cnt1|cntout1[2]~1_combout\);

-- Location: FF_X32_Y24_N21
\cnt1|cntout1[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div1|clkout~clkctrl_outclk\,
	d => \cnt1|cntout1[2]~1_combout\,
	clrn => \ALT_INV_rst~inputclkctrl_outclk\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \cnt1|cntout1\(2));

-- Location: LCCOMB_X32_Y24_N26
\cnt1|cntout1~2\ : cycloneiv_lcell_comb
-- Equation(s):
-- \cnt1|cntout1~2_combout\ = (\cnt1|cntout1\(1) & (\cnt1|cntout1\(3) $ (((\cnt1|cntout1\(0) & \cnt1|cntout1\(2)))))) # (!\cnt1|cntout1\(1) & (\cnt1|cntout1\(3) & ((\cnt1|cntout1\(2)) # (!\cnt1|cntout1\(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0111100010110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout1\(1),
	datab => \cnt1|cntout1\(0),
	datac => \cnt1|cntout1\(3),
	datad => \cnt1|cntout1\(2),
	combout => \cnt1|cntout1~2_combout\);

-- Location: FF_X32_Y24_N27
\cnt1|cntout1[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div1|clkout~clkctrl_outclk\,
	d => \cnt1|cntout1~2_combout\,
	clrn => \ALT_INV_rst~inputclkctrl_outclk\,
	ena => \cnt1|Equal0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \cnt1|cntout1\(3));

-- Location: LCCOMB_X32_Y24_N22
\cnt1|cntout1~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \cnt1|cntout1~0_combout\ = (\cnt1|cntout1\(0) & (!\cnt1|cntout1\(1) & ((\cnt1|cntout1\(2)) # (!\cnt1|cntout1\(3))))) # (!\cnt1|cntout1\(0) & (((\cnt1|cntout1\(1)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000110100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout1\(3),
	datab => \cnt1|cntout1\(0),
	datac => \cnt1|cntout1\(1),
	datad => \cnt1|cntout1\(2),
	combout => \cnt1|cntout1~0_combout\);

-- Location: FF_X32_Y24_N23
\cnt1|cntout1[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \div1|clkout~clkctrl_outclk\,
	d => \cnt1|cntout1~0_combout\,
	clrn => \ALT_INV_rst~inputclkctrl_outclk\,
	ena => \cnt1|Equal0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \cnt1|cntout1\(1));

-- Location: LCCOMB_X32_Y25_N24
\dec|Mux6~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \dec|Mux6~0_combout\ = (\cnt1|cntout1\(3)) # ((\cnt1|cntout1\(1) & ((!\cnt1|cntout1\(2)) # (!\cnt1|cntout1\(0)))) # (!\cnt1|cntout1\(1) & ((\cnt1|cntout1\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111011111111010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout1\(1),
	datab => \cnt1|cntout1\(0),
	datac => \cnt1|cntout1\(3),
	datad => \cnt1|cntout1\(2),
	combout => \dec|Mux6~0_combout\);

-- Location: LCCOMB_X32_Y25_N2
\dec|Mux5~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \dec|Mux5~0_combout\ = (!\cnt1|cntout1\(3) & ((\cnt1|cntout1\(1) & ((\cnt1|cntout1\(0)) # (!\cnt1|cntout1\(2)))) # (!\cnt1|cntout1\(1) & (\cnt1|cntout1\(0) & !\cnt1|cntout1\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000100000001110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout1\(1),
	datab => \cnt1|cntout1\(0),
	datac => \cnt1|cntout1\(3),
	datad => \cnt1|cntout1\(2),
	combout => \dec|Mux5~0_combout\);

-- Location: LCCOMB_X32_Y25_N20
\dec|Mux4~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \dec|Mux4~0_combout\ = (\cnt1|cntout1\(1) & (\cnt1|cntout1\(0) & (!\cnt1|cntout1\(3)))) # (!\cnt1|cntout1\(1) & ((\cnt1|cntout1\(2) & ((!\cnt1|cntout1\(3)))) # (!\cnt1|cntout1\(2) & (\cnt1|cntout1\(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110101001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout1\(1),
	datab => \cnt1|cntout1\(0),
	datac => \cnt1|cntout1\(3),
	datad => \cnt1|cntout1\(2),
	combout => \dec|Mux4~0_combout\);

-- Location: LCCOMB_X32_Y25_N6
\dec|Mux3~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \dec|Mux3~0_combout\ = (!\cnt1|cntout1\(3) & ((\cnt1|cntout1\(1) & (\cnt1|cntout1\(0) & \cnt1|cntout1\(2))) # (!\cnt1|cntout1\(1) & (\cnt1|cntout1\(0) $ (\cnt1|cntout1\(2))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000100100000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout1\(1),
	datab => \cnt1|cntout1\(0),
	datac => \cnt1|cntout1\(3),
	datad => \cnt1|cntout1\(2),
	combout => \dec|Mux3~0_combout\);

-- Location: LCCOMB_X32_Y25_N4
\dec|Mux2~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \dec|Mux2~0_combout\ = (\cnt1|cntout1\(2) & (((\cnt1|cntout1\(3))))) # (!\cnt1|cntout1\(2) & (\cnt1|cntout1\(1) & ((\cnt1|cntout1\(3)) # (!\cnt1|cntout1\(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000010100010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout1\(1),
	datab => \cnt1|cntout1\(0),
	datac => \cnt1|cntout1\(3),
	datad => \cnt1|cntout1\(2),
	combout => \dec|Mux2~0_combout\);

-- Location: LCCOMB_X32_Y25_N22
\dec|Mux1~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \dec|Mux1~0_combout\ = (\cnt1|cntout1\(3) & ((\cnt1|cntout1\(1)) # ((\cnt1|cntout1\(2))))) # (!\cnt1|cntout1\(3) & (\cnt1|cntout1\(2) & (\cnt1|cntout1\(1) $ (\cnt1|cntout1\(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111011010100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout1\(1),
	datab => \cnt1|cntout1\(0),
	datac => \cnt1|cntout1\(3),
	datad => \cnt1|cntout1\(2),
	combout => \dec|Mux1~0_combout\);

-- Location: LCCOMB_X32_Y25_N12
\dec|Mux0~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \dec|Mux0~0_combout\ = (!\cnt1|cntout1\(1) & (!\cnt1|cntout1\(3) & (\cnt1|cntout1\(0) $ (\cnt1|cntout1\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000100000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout1\(1),
	datab => \cnt1|cntout1\(0),
	datac => \cnt1|cntout1\(3),
	datad => \cnt1|cntout1\(2),
	combout => \dec|Mux0~0_combout\);

-- Location: LCCOMB_X32_Y24_N12
\dec|Mux13~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \dec|Mux13~0_combout\ = (\cnt1|cntout2\(3)) # ((\cnt1|cntout2\(1) & ((!\cnt1|cntout2\(2)) # (!\cnt1|cntout2\(0)))) # (!\cnt1|cntout2\(1) & ((\cnt1|cntout2\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011111111101110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout2\(3),
	datab => \cnt1|cntout2\(1),
	datac => \cnt1|cntout2\(0),
	datad => \cnt1|cntout2\(2),
	combout => \dec|Mux13~0_combout\);

-- Location: LCCOMB_X32_Y24_N10
\dec|Mux12~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \dec|Mux12~0_combout\ = (!\cnt1|cntout2\(3) & ((\cnt1|cntout2\(1) & ((\cnt1|cntout2\(0)) # (!\cnt1|cntout2\(2)))) # (!\cnt1|cntout2\(1) & (\cnt1|cntout2\(0) & !\cnt1|cntout2\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100000001010100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout2\(3),
	datab => \cnt1|cntout2\(1),
	datac => \cnt1|cntout2\(0),
	datad => \cnt1|cntout2\(2),
	combout => \dec|Mux12~0_combout\);

-- Location: LCCOMB_X32_Y24_N16
\dec|Mux11~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \dec|Mux11~0_combout\ = (\cnt1|cntout2\(1) & (!\cnt1|cntout2\(3) & (\cnt1|cntout2\(0)))) # (!\cnt1|cntout2\(1) & ((\cnt1|cntout2\(2) & (!\cnt1|cntout2\(3))) # (!\cnt1|cntout2\(2) & ((\cnt1|cntout2\(0))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101000101110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout2\(3),
	datab => \cnt1|cntout2\(1),
	datac => \cnt1|cntout2\(0),
	datad => \cnt1|cntout2\(2),
	combout => \dec|Mux11~0_combout\);

-- Location: LCCOMB_X32_Y24_N6
\dec|Mux10~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \dec|Mux10~0_combout\ = (!\cnt1|cntout2\(3) & ((\cnt1|cntout2\(1) & (\cnt1|cntout2\(0) & \cnt1|cntout2\(2))) # (!\cnt1|cntout2\(1) & (\cnt1|cntout2\(0) $ (\cnt1|cntout2\(2))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100000100010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout2\(3),
	datab => \cnt1|cntout2\(1),
	datac => \cnt1|cntout2\(0),
	datad => \cnt1|cntout2\(2),
	combout => \dec|Mux10~0_combout\);

-- Location: LCCOMB_X32_Y24_N8
\dec|Mux9~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \dec|Mux9~0_combout\ = (\cnt1|cntout2\(2) & (\cnt1|cntout2\(3))) # (!\cnt1|cntout2\(2) & (\cnt1|cntout2\(1) & ((\cnt1|cntout2\(3)) # (!\cnt1|cntout2\(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010101010001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout2\(3),
	datab => \cnt1|cntout2\(1),
	datac => \cnt1|cntout2\(0),
	datad => \cnt1|cntout2\(2),
	combout => \dec|Mux9~0_combout\);

-- Location: LCCOMB_X32_Y24_N2
\dec|Mux8~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \dec|Mux8~0_combout\ = (\cnt1|cntout2\(3) & ((\cnt1|cntout2\(1)) # ((\cnt1|cntout2\(2))))) # (!\cnt1|cntout2\(3) & (\cnt1|cntout2\(2) & (\cnt1|cntout2\(1) $ (\cnt1|cntout2\(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011111010001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout2\(3),
	datab => \cnt1|cntout2\(1),
	datac => \cnt1|cntout2\(0),
	datad => \cnt1|cntout2\(2),
	combout => \dec|Mux8~0_combout\);

-- Location: LCCOMB_X32_Y24_N24
\dec|Mux7~0\ : cycloneiv_lcell_comb
-- Equation(s):
-- \dec|Mux7~0_combout\ = (!\cnt1|cntout2\(3) & (!\cnt1|cntout2\(1) & (\cnt1|cntout2\(0) $ (\cnt1|cntout2\(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000100010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \cnt1|cntout2\(3),
	datab => \cnt1|cntout2\(1),
	datac => \cnt1|cntout2\(0),
	datad => \cnt1|cntout2\(2),
	combout => \dec|Mux7~0_combout\);

ww_out1(0) <= \out1[0]~output_o\;

ww_out1(1) <= \out1[1]~output_o\;

ww_out1(2) <= \out1[2]~output_o\;

ww_out1(3) <= \out1[3]~output_o\;

ww_out1(4) <= \out1[4]~output_o\;

ww_out1(5) <= \out1[5]~output_o\;

ww_out1(6) <= \out1[6]~output_o\;

ww_out2(0) <= \out2[0]~output_o\;

ww_out2(1) <= \out2[1]~output_o\;

ww_out2(2) <= \out2[2]~output_o\;

ww_out2(3) <= \out2[3]~output_o\;

ww_out2(4) <= \out2[4]~output_o\;

ww_out2(5) <= \out2[5]~output_o\;

ww_out2(6) <= \out2[6]~output_o\;

ww_h(0) <= \h[0]~output_o\;

ww_h(1) <= \h[1]~output_o\;

ww_h(2) <= \h[2]~output_o\;

ww_h(3) <= \h[3]~output_o\;

ww_l(0) <= \l[0]~output_o\;

ww_l(1) <= \l[1]~output_o\;

ww_l(2) <= \l[2]~output_o\;

ww_l(3) <= \l[3]~output_o\;
END structure;


